1. Field of the Invention
The present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory), and in particular to a semiconductor memory device compatible with the data of a plurality of types of bit configuration, such as xc3x9716 bit (16 bit width) configuration, xc3x978 bit (8 bit width) configuration and xc3x974 bit (4 bit width) configuration.
2. Description of the Related Art
Conventionally, large capacity semiconductor memory devices as represented by DRAM are constructed to be compatible with multiple types of data from varying bit configurations, such as xc3x9716 bit configurations, xc3x978 bit configurations and xc3x974 bit configurations by adaptation during the manufacturing process, in order to meet the needs of a variety of users.
However, despite the large increase in the capacity of semiconductor memory devices due to improvements in refined manufacturing technology, some users may demand semiconductor memory devices with even larger memory capacity. For example, the currently most common 256 megabit DRAM is compatible with three types of bit configuration, xc3x9716 bit configuration, xc3x978 bit configuration and xc3x974 bit configuration. However depending on the user, there may be a situation where for example 512 megabits memory capacity is needed in an xc3x974 bit configuration.
In order to satisfy the needs of this kind of user, it would be satisfactory to develop a new semiconductor memory device that has more memory capacity, but developing a new semiconductor memory device requires time, and these needs cannot be satisfied quickly.
As an alternative technology until a new semiconductor memory device is developed, for example, a method has been proposed where a conventional semiconductor memory device which is compatible with data of an xc3x972 bit (2 bit width) configuration in addition to the aforementioned three types of bit configuration is constructed, and two of these semiconductor memory devices are then used to realize the appearance of an xc3x974 bit configuration semiconductor memory device of increased capacity.
FIG. 7 shows a sample construction of a data write system of a semiconductor memory device that in addition to the aforementioned three types of bit configuration, namely xc3x9716 bit configuration, xc3x978 bit configuration and xc3x974 bit configuration, is also compatible with xc3x972 bit configuration. The semiconductor memory device shown in this diagram includes data input circuits (DIN in the figure) 700-715 for inputting 16 bit data DQ0-DQ15 from an external source, and data write circuits (WAMP in the figure) 800-815 for writing the data input by the data input circuits to a memory cell array 900.
The data output from the data input circuit 700 is distributed to eight data write circuits 800-803 and 812-815. The data output from the data input circuit 701 is distributed only to the data write circuit 801, the data output from the data input circuit 702 is distributed to two data write circuits 802, 803, and the data output from the data input circuit 703 is distributed only to the data write circuit 803. The data output from the data input circuit 715 is distributed to four data write circuits 812-815, the data output from the data input circuit 714 is distributed only to the data write circuit 814, the data output from the data input circuit 713 is distributed to two data write circuits 812, 813, and the data output from the data input circuit 712 is distributed only to the data write circuit 812.
Similarly, the data output from the data input circuit 704 is distributed to eight data write circuits 804-811, the data output from the data input circuit 705 is distributed only to the data write circuit 805, the data output from the data input circuit 706 is distributed to two data write circuits 806 and 807, and the data output from the data input circuit 707 is distributed only to the data write circuit 807. The data output from the data input circuit 711 is distributed to four data write circuits 808-811, the data output from the data input circuit 710 is distributed only to the data write circuit 810, the data output from the data input circuit 709 is distributed to two data write circuits 808, 809, and the data output from the data input circuit 708 is distributed only to the data write circuit 808.
Of the sixteen data write circuits 800-815, a mask signal LWM for masking the writing of the lower 8 bits of the 16 bit data DQ0-DQ15 which is input from an external source, is input into the data write circuits 800-807. A mask signal UWM for masking the writing of the upper 8 bits of the 16 bit data DQ0-DQ15, is input into the data write circuits 808-815.
FIG. 8 shows the structure of a mask signal generation circuit 850 for generating the upper bit range mask signal UWM and the lower bit range mask signal LWM.
In FIG. 8, a mask control signal UDQM for the upper 8 bits, which is received from an external source, is received by an input circuit 851 and is then output via a buffer consisting of inverters 852 and 853 to the data write circuits 808-815 shown in FIG. 7 as the mask signal UWM. Furthermore, a mask control signal LDQM for the lower 8 bits, which is received from an external source, is received by an input circuit 854 and is then output via a buffer consisting of inverters 855 and 856 to the data write circuits 800-807 shown in FIG. 7 as the mask signal LWM.
In this example, in the handling of 16 bit data, the mask signal UWM and the mask signal LWM are activated complementarily, and the data write circuits 800-807 and the data write circuits 808-915 are controlled complementarily. Consequently, of the 16 bit data DQ0-DQ15, the writing of the lower 8 bit range data DQ0-DQ7 and the upper 8 bit range data DQ8-DQ15 are respectively masked. Furthermore, in the handling of 2 bit data, 4 bit data, and 8 bit data, then as shown in the construction of FIG. 8, as a result of the formation of a signal path PJ from the input circuit 851 to the input circuit 854, the mask signal UWM and the mask signal LWM become equivalent, and only the mask control signal UDQM, which is received from an external source, is valid. In this case, for data from each of an xc3x972 bit configuration, an xc3x974 bit configuration and an xc3x978 bit configuration, the mask control signal UDQM controls whether or not the writing of all bits will be masked.
In FIG. 7, the memory cell array 900 incorporates an address signal map which is used according to the bit configuration of the data to be stored. In this example, when 16 bit data is to be stored, none of address signals Y9, Y11, Y12 are used, and the 16 bit data output from the data write circuits 800-815 is written directly to the memory cell array 900. Furthermore, when 8 bit data is stored, either the data write circuits 801, 803, 805, 807, 808, 810, 812, 814, or the data write circuits 800, 802, 804, 806, 809, 811, 813, 815 are selected by the address signal Y9. In this case, the address signals Y11, Y12 are not used.
In addition, when 4 bit data is stored, either the data write circuits 802, 803, 806, 807, 808, 809, 812, 813 or the data write circuits 800, 801, 804, 805, 810, 811, 814, 815 are selected according to the address signal Y11, and one quarter of the totality of data write circuits are selected by the address signals Y9 and Y11. In this case the address signal Y12 is not used. Furthermore, when 2 bit data is stored, either the data write circuits 800-807 or the data write circuits 808-815 are selected according to the address signal Y12, and one eighth of the totality of data write circuits are selected according to the address signals Y9, Y11 and Y12.
Although not shown in the figure, the data output from the data write circuits selected by the address signals Y9, Y11 and Y12 is written to a predetermined memory cell in the memory cell array 900 based on other address signals.
In conventional semiconductor memory devices with this kind of structure, when, for example, 16 bit data is to be stored in memory, the data write circuit 800 receives the data output from the data input circuit 700, and the data write circuit 801 receives the data output from the data input circuit 701, and in this manner the circuits are produced in the manufacturing process so that the data write circuits 800-815 each receive the data output from one corresponding data input circuit.
Furthermore when, for example, 8 bit data is to be stored in memory, the data write circuits 800, 801 receive the data output from the data input circuit 700, and the data write circuits 802, 803 receive the data output from the data input circuit 702, and in this manner the circuits are produced in the manufacturing process so that the data output from one data input circuit is received by two data write circuits.
Moreover, when 4 bit data is to be stored in memory, the data write circuits 800-803 receive the data output from the data input circuit 700, and the data write circuits 812-815 receive the data output from the data input circuit 715, and in this manner the circuits are produced in the manufacturing process so that the data output from one data input circuit is received by four data write circuits.
Furthermore, when 2 bit data is to be stored in memory, the data write circuits 800-803 and 812-815 receive the data output from the data input circuit 700, and data write circuits 804-811 receive the data output from data input circuit 704, and in this manner the circuits are produced in the manufacturing process so that the data output from one data input circuit is received by eight data write circuits.
In the above example, when 8 bit data is to be stored in memory, the decision as to which of the data write circuits 800, 801, which both receive common data output from the data input circuit 700, will provide data to be written to the memory cell array 900, is determined based on an externally received column address signal.
However, according to the aforementioned conventional semiconductor memory device, the data is distributed directly from the data input circuit to the data write circuit based on the bit configuration of the data to be stored. As a result, a problem arises in that the output load of a specific data input circuit shared by a plurality of bit configurations will increase markedly, causing delays in the data when data is being written.
For example, in the example shown in FIG. 7, in order to be compatible with xc3x972 bit configuration, the data output from the specific data input circuit 700 must be distributed to the eight data write circuits 800-803 and 812-815, and this means that the output load of the data input circuit 700 will increase markedly. As a result, even when other bit configurations such as xc3x974 bit configurations are taken, the output load of the specific data input circuit 700 increases, and the data DQ0 is delayed at the time of writing. In the example shown in FIG. 7, the same can be said for the data input circuit 704.
Furthermore, when the variety of bit configuration types increases, the map incorporated in the memory cell array 900 shown in FIG. 7 becomes more complex. Consequently, another problem arises in that that the circuitry used to determine which of the plurality of data write circuits will provide the output data which is ultimately written to the memory cell array becomes more complex.
In view of the above circumstances, an object of the present invention is to provide a semiconductor memory device which is capable of handling data of various bit configurations, without causing any delay in the writing of data due to an increased output load of a specific data input circuit, and where circuitry that determines which data is ultimately written to a memory cell array does not become more complex even when the variety of bit configurations increases.
In order to achieve this object, the present invention is of a construction described below.
A semiconductor memory device according to the present invention is a semiconductor memory device which is compatible with data (for example, elements corresponding with data DQ0-DQ15 described below) of a plurality of types of bit configuration (for example, xc3x972 bit configuration, xc3x974 bit configuration, xc3x978 bit configuration, and xc3x9716 bit configuration as described below), and which comprises; a plurality of data input circuits (for example, components corresponding with data input circuits 100-115 described below) for inputting data from an external source, a memory cell for storing data (for example, memory cell array 300 described below), and a plurality of data write circuits (for example, structural elements corresponding with data write circuits 200-215 described below) for writing the data input from the plurality of data input circuits to the memory cell, wherein data to be stored is input from the external source by selectively using the plurality of data input circuits, and then each bit of the data to be stored is distributed to the plurality of the data write circuits according to a bit configuration of the data, and furthermore of the plurality of data input circuits, data input from a specific data input circuit (for example, components corresponding with data input circuits 100, 104 described below) is distributed to one of the plurality of data write circuits via another data input circuit (for example, components corresponding with data input circuits 115, 111 described below).
According to this construction, data output from a specific data input circuit is input into another data input circuit, and is then distributed to a data write circuit via this other data input circuit. In this manner, by distributing data from a specific data input circuit to another data input circuit, the need to directly distribute the data from the specific data input circuit to the data write circuit which inputs data from the other data input circuit is eliminated. Consequently, the number of data write circuits that make up the output load of the specific data input circuit is lowered, and the output load of this specific data input circuit is reduced. As a result, compatibility with various bit configurations becomes possible without the output load of the specific data input circuit increasing and a delay in the writing of data occurring.
Furthermore, with a semiconductor memory device according to the present invention, a mask control circuit (for example, components corresponding with a mask signal generation circuit 600 described below) for masking writing of data received from the external source by the plurality of data input circuits may be included as an option.
According to this construction, it becomes possible to mask the writing of each bit of data from a plurality of bit configurations, and a variety of data writing configurations can be used.
Moreover, in a semiconductor memory device according to the present invention, the mask control circuit may selectively control the plurality of data write circuits and mask writing of the data based on an externally received predetermined mask signal (for example, signal elements corresponding with mask control signals UDQM, LDQM described below).
According to such a construction, the data input to a plurality of data write circuits from a plurality of data input circuits is selectively written to the memory cell array based on the predetermined mask signal. Consequently, masking the writing of a portion of the bits of the data input from an external source by the plurality of data input circuits becomes possible.
Furthermore, in a semiconductor memory device according to the present invention, a specific address signal (for example, signal elements corresponding with address signals Y9, Y11, Y12 described below) used according to the plurality of types of bit configuration, may influence a signal used to mask writing of the data.
According to such a construction, the data input into the plurality of data write circuits from the plurality of data input circuits is selectively written to the memory cell array based on the specific address signal used according to the plurality of bit configurations. Consequently, it becomes possible to select output data from the data write circuit according to the bit configuration and write the data to the memory cell array without increasing the devices for selecting the output data of the data write circuit. Therefore, even if the variety of bit configurations increases, the circuitry (for example, circuitry for realizing a map incorporated in a memory cell array 300 shown in the appended diagrams of FIG. 1 and FIG. 2) for selecting which data will ultimately be written to the memory cell array need not become more complex.
Furthermore, in a semiconductor memory device according to the present invention, the specific data input circuit may be used for the data of all of the plurality of types of bit configuration.
According to such a construction, the data that is distributed to the highest number of data write circuits is distributed to a plurality of data write circuits via another data input circuit. Consequently, the output load of the specific data input circuit that outputs this data is reduced.
Furthermore, in a semiconductor memory device according to the present invention, another data input circuit may be used for data of all bit configurations from the plurality of types of bit configuration, with an exception of the bit configuration which has the fewest number of bits.
According to such a construction, the data output of a specific data input circuit is distributed to all the data write circuits that are used for data of other bit configurations and data of the bit configuration with the fewest number of bits, via another data input circuit. Consequently, it becomes possible for the data output of a specific data input circuit to be distributed to the data write circuit via a minimum number of other data input circuits.
Furthermore, in a semiconductor memory device according to the present invention, the specific data input circuit may be used for data of all of the plurality of types of bit configuration, and another data input circuit may be used for data of all bit configurations from the plurality of types of bit configuration, with an exception of the bit configuration which has the fewest number of bits.
According to such a construction, the data that is distributed to the most data write circuits is distributed to a plurality of data write circuits via another data input circuit. Consequently, the load placed on the specific data input circuit that outputs this data is reduced. Furthermore, the data output of a specific data input circuit is distributed to all the data write circuits that are used for data of other bit configurations and data of the bit configuration with the fewest number of bits, via another data input circuit. Consequently, it becomes possible for the data output of a specific data input circuit to be distributed to the data write circuit via the minimum number of other data input circuits.
Furthermore, in a semiconductor memory device according to the present invention, another data input circuits may be equipped with; an input buffer section (for example, components corresponding with an input buffer section 115A described below) for inputting data from the external source, a selection section (for example, components corresponding with selection section 115B described below) for selecting data input from either one of the input buffer section and the specific data input circuit, and a driver section (for example, components corresponding with a driver section 115C described below) for outputting data selected by the selection section to one of the plurality of data write circuits.
According to such a construction, data from an external source is received by the input buffer section in another data input circuit. Here, data input by the specific data input circuit, after being selected by the selection section, is output to the data write circuit via the driver section. Consequently, it becomes possible for data output from a specific data input circuit to be distributed to one of a plurality of data write circuits via another data input circuit.
Furthermore, in a semiconductor memory device according to the present invention, the selection section may be constructed so that, during a manufacturing process of a semiconductor memory device, an input section of the driver section may be electrically connected with an output section of either one of the input buffer section and the specific data input circuit.
According to such a construction, semiconductor memory devices compatible with each variety of bit configuration can be differentiated in the manufacturing process. Consequently, the bit configuration of the data to be stored is fixed at the time of manufacture, and the user who will use this semiconductor memory device does not need to set the state of the circuitry in accordance with the bit configuration of the data to be stored.